The present invention relates generally to integrated circuit chip fabrication, and more specifically to a technique for fabricating logical and memory elements using a multiple gate layer technique.
The fabrication of an integrated circuit typically involves a variety of steps including a design phase, multiple simulation phases, and a fabrication phase. During the design phase, the various logical components of the integrated circuit (IC) are incorporated into a unified design layout, typically with the help of integrated circuit design software. Thereafter, during a simulation phase, the integrated circuit design is tested using conventional circuit simulation software such as, for example, spice parameter extraction software. Examples of spice parameter extraction software include BSIMPRO (licensed by Celestry Design Technologies, Inc., of San Jose, Calif.), and Aurora (licensed by Synopsys, Inc., of Mountain View, Calif.). During the fabrication stage of the integrated circuit, a variety of IC structures may be formed on a silicon wafer by forming layers on and removing various layered regions from the silicon wafer.
Generally, it is desirable to reduce the costs and expenses associated with integrated circuit (IC) chip fabrication. A conventional technique for reducing IC chip fabrication costs involves reducing the number of deposition and etching steps which are performed during the IC chip fabrication process. For this reason, it is the conventional practice in the industry to fabricate integrated circuits using only a single layer of deposited poly-silicon. Such a technique provides for a relatively less complex and cheaper fabrication process. In fact, the use of a single poly-silicon layer in the fabrication of logic elements (which form part of an integrated circuit) is so widely accepted that most conventional circuit simulation software currently available on the market are primarily designed to be compatible with standardized layout and fabrication techniques which use a single poly-silicon layer.
Examples of a portion of a conventional integrated circuit design are illustrated in FIGS. 1A-C of the drawings. FIG. 1A shows a schematic diagram of a circuit 100 which includes two transistors that are connected in series (herein referred to as “series transistor circuit”). When incorporated as part of an integrated circuit using conventional IC fabrication techniques, the series transistor circuit 100 of FIG. 1A may be fabricated as illustrated in FIG. 1B. As illustrated in FIG. 1B, the circuit portion 150 includes two serially connected transistors which have been fabricated using a single poly-silicon layer. More specifically, as shown in FIG. 1B, the circuit portion 150 includes two gate portions 102a, 102b which have both been fabricated using a single poly-silicon layer. Additionally, circuit portion 150 also includes two oxide layer portions 104a, 104b, which have both been fabricated using a single oxide layer. The circuit portion 150 further includes a substrate 110 (e.g., silicon substrate), which includes three doped regions 105a, 105b, 105c formed within a doped well region 108. In the example of FIG. 1B, the circuit portion 150 has been configured as two serially connected NMOS transistors, which include P-well region 108, and N+ doped regions 105a-c. Such a circuit may be used, for example, in the formation of a variety of conventional logic elements such as NOR gates, NAND gates, etc.
FIG. 1C shows an example of a conventional IC design layout 170 of the series transistor circuit 100 of FIG. 1A. As illustrated in FIG. 1C, the conventional technique for fabricating the series transistor circuit 100 is performed using a single poly-silicon layering technique, wherein gates 102a and 102b are formed over an active region 115 of the transistor circuit. Each of the gates 102a, 102b is formed from the same poly-silicon layer. Using conventional terminology, gates 102a and 102b may each be described as being composed of “poly1” material since each of these gates are formed from the same first layer of deposited poly-silicon (i.e., poly-1). According to conventional design rules, each of the gates 102a and 102b are required to be separated by a minimum distance 117 in order to ensure proper operation of the fabricated circuit.
While the use of a single poly-silicon layer conforms with standardized IC layout and fabrication techniques, such standardized techniques necessitate specific design and layout requirements which may result in an inefficient utilization of space on the silicon wafer or substrate. Accordingly, it will be appreciated that there exists a continual need to improve upon integrated circuit chip fabrication techniques in order to accommodate and take advantage of new and emerging technologies.